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| MC33889 advance information system basis chip with low speed fault tolerant can interface system basis chip silicon monolithic integrated circuit pin connections dw suffix plastic package case so-28 simplified block diagram ordering information device operating temperature range package so-28 t a = -40 to 125c none vdd1 rx canh vsup rth canl sclk tx gnd gnd gnd gnd gnd intb 1 2 3 5 4 6 7 8 10 28 19 20 21 22 23 24 25 26 27 rtl l1 reset l0 csb gnd 11 12 14 9 13 18 17 15 16 miso mosi gnd hs1 gnd v2ctrl wdogb v2sense (top view) semiconductor technical data motorola order number: MC33889/d rev. 5.0, 08/2001 this document contains information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc., 2001. all rights reserved. tm the MC33889 is a monolithic integrated circuit combining many functions frequently used by automotive ecus. it incorporates a low speed fault tolerant can physical inteface. main features: ?vdd1: low drop voltage regulator, current limitation, over temperature detection, monitoring and reset function. total current capability 200ma (100ma for can current plus 100ma for mcu and external peripheral components). ?v2: control circuitry for external bipolar ballast transistor for high flexibility in choice of peripheral voltage and current supply. ?four operational modes: normal, stand-by, stop and sleep modes. ?low stand-by current consumption in stop and sleep modes ?built in low speed 125kbaud fault tolerant can physical interface, compatible with motorola mc33388. ?external high voltage wake-up input, associated with hs1 vbat switch ?150ma output current capability for hs1 vbat switch allowing drive of external switches pull up resistors or relays ?vsup monitoring and failure detection ?dc operating voltage from 5 to 27v ?40v maximum transient voltage ?programmable software time out and window watchdog ?separate outputs for watchdog time out signla (wdogb) and reset (reset). ?wake up capabilities: wake up input, programmable cyclic sense, forced wake up, can interface and spi (csb pin). ?interface with mcu through 4 mhz spi. ?so28wb package with thermal enhanced lead frame. programmable spi interface dual voltage regulator vsup monitor vdd1 monitor hs1 control mode control reset watchdog wake-up input csb sclk mosi reset intb 5v/200ma v2ctrl vdd1 hs1 oscillator v2sense v2 wdogb vsup vdd1 interupt vbat r1 r2 q1 l0 l1 miso rxd txd low speed 125kbit/s physical interface can l can h rrth rth rtl rrtl fault tolerant can gnd 5v/100ma can supply
MC33889 system basis chip with low speed fault tolerant can interface 2 1 maximum ratings ratings symbol min typ max unit electrical ratings supply voltage at vsup - continuous voltage - transient voltage (load dump) vsup vsup -0.3 27 40 v logic inputs (rx, tx, mosi, miso, csb, sclk, reset, wdogb, intb) vlog - 0.3 vdd1+0.3 v output current vdd1 i internally limited a hs1 - voltage - output current v i -0.3 internally limited vsup+0.3 v a esd voltage (hbm 100pf, 1.5k) - canl, canh, rtl, rth, hs1, l0, l1 - all other pins vesdh -4 -2 4 2 kv esd voltage (machine model) all pins vesdm 200 200 v l0, l - dc input voltage - dc input current - transient input current (according to iso7637 specifi- cation) and with external component tbd. vwu dc -0.3 -2 tbd 40 2 tbd v ma ma can related pins: canh, canl, rtl, rth, tx, rx (refer to can section) thermal ratings junction temperature t j - 40 +150 c storage temperature t s - 55 +165 c ambient temperature (for info only) t a - 40 +125 c thermal resistance junction pin rthj/p 20 c/w MC33889 system basis chip with low speed fault tolerant can interface 3 2 electrical characteristics (v sup from 5.5v to 18v and t j from -40c to 150c) unless otherwise noted. for all pins except can related pins description symbol characteristics unit conditions min typ max vsup pin (device power supply) nominal dc voltage range vsup 5.5 18 v extended dc voltage range 1 vsup-ex1 4.5 5.5 v reduced functionality (note 1) extended dc voltage range 2 vsup-ex2 18 27 v (note 3) input voltage during load dump vsupld 40 v load dump situation input voltage during jump start vsupjs 27 v jump start situation supply current in sleep mode (note 2,4) isup (sleep1) 45 65 m a vdd1 & v2 off, vsup<12v, oscillator running (note 5) excluding can current supply current in sleep mode (note 2,4) isup (sleep2) 25 40 m a vdd1 & v2 off, vsup<12v oscillator not running (note5) excluding can current , supply current in sleep mode (note 2,4) isup (sleep3) 150 m a vdd1 & v2 off, vsup>12v oscillator running (note 5) excluding can current supply current in stand-by mode (note 2,4) isup(stdby) 15 ma iout at vdd1 =10ma, can recessive state or disabled supply current in normal mode (note 2) isup(norm) 15 ma iout at vdd1 =10ma, can recessive state or disabled supply current in stop mode (note 2,4) i out vdd1 <2ma isup (stop1) 85 m a vdd1 on (note 6) , vsup<12v oscillator running (note 5) excluding can current , supply current in stop mode (note 2,4) iout vdd1 < 2ma isup (stop2) 60 m a vdd1 on (note 6) , vsup<12v oscillator not running (note 5) excluding can current supply current in stop mode (note 2,4) iout vdd1 < 2ma isup (stop2) 1 80 m a vdd on (note6) , vsup>12 oscillator running (note 5) excluding can current supply fail flag internal threshold vthresh 1.5 3 4 v supply fail flag hysteresis vdet hyst 1 v note 1: vdd1>4v, reset high, logic pin high level reduced, device is functional. note 2: current measured at vsup pin. note 3 : device is fully functional. all mode s available and operating, watchdog, hs1 turn on turn off, can cell operating, l0 and l 1 input operating, spi read write operation. over temperature may occur. note 4: excluding the can cell current. a n additional 3 0ua typical must be added to specified value. note 5: oscillator running means ?forced wake up? or ?cyclic sense? or ?software watchdog? timer activated. note 6: vdd is on with2ma typical output current capability. vdd1 (external 5v output for mcu supply and internal can physical interface supply). idd1 is the total regulator output current. iddcan is the internal can block supply current. iout is vdd1 external output curren t. idd1 = iddcan + iout. vdd specification with external capacitor c>1uf and esr<1o ohm. no tantalum capacitor required. vdd1 output voltage vdd1out 4,9 5 5,1 v idd 1 from 2 to 200ma 5.5v< vsup <27v vdd1 output voltage vdd1out 4 v idd 1 from 2 to 200ma 4.5v< vsup <5.5v drop voltage vsup>vddout vdd1drop 0.2 0,5 v idd 1 = 200ma idd1 current (idd1 = iddcan + iout) idd1 200 270 350 ma internally limited included internal can current consumption vdd1 output voltage in stop mode vddstop 4,75 5,00 5,25 v iout < 2ma thermal shutdown tsd 160 190 c MC33889 system basis chip with low speed fault tolerant can interface 4 over temperature pre warning tpw 130 160 c temperature threshold difference tsd-tpw 20 40 c reset threshold 1 rst-th1 4.3 4.5 v 4.7 selectable by spi. default value after reset. reset threshold 2 rst-th2 3.6 3.8 4 selectable by spi reset duration reset-dur 1 2 ms vdd1 range for reset active vdd r 1 v reset delay time t d 5 20 m s line regulation lr1 5 25 mv 9v MC33889 system basis chip with low speed fault tolerant can interface 7 3 can module specification (compatible with mc33388) electrical ratings electrical characteristics (v sup from 5.5v to 18v and t j from -40c to 150c unless otherwise noted). ratings symbol min typ max unit dc voltage on pins tx, rx vlogic -0.3 v dd1 + 0.3 v dc voltage on pins canh, canl v bus -20 +27 v transient voltage at pins canh, canl 0 < v dd < 5.5v ; v sup 3 0 ; t < 500ms v canh /v canl -40 40 v transient voltage on pins canh, canl (coupled through 1nf capacitor) v tr -150 100 v dc voltage on pins rth, rtl v rtl , v rth -0.3 +27 v transient voltage at pins rth, rtl 0 < v dd < 5.5v ; v sup 3 0 ; t < 500ms v rth /v rtl -0.3 40 v rth, rtl termination resistance r t 500 16000 w conditions symbol min typ max unit supply current described below are the can module internal supply current from vdd and vsup internal vdd supply current (can and sbc in normal mode). tx= vdd, can in recessive state i vdd1-int 2.3 3 ma internal vdd supply current (can and sbc in normal mode). tx = 0v, no load, can in dominant state i vdd1-int 3.3 5 ma vsup supply current (can and sbc in normal mode). tx = vdd i sup-int 150 300 m a total supply current (can in receive only mode, sbc in normal mode). vdd = 5v ; v sup = 12v i vdd1-int + i bat-int 0.85 1.2 ma total supply current (can in bus standby mode, sbc in normal mode). vdd = 5v ; v sup = 12v i vdd1-int + i bat-int 20 40 m a vbat supply current (can in bus standby mode) vdd = 0v ; v sup = 12v i bat 15 25 m a tx pin high level input voltage v ih 0.7*v dd1 v dd1 +0.3v v low level input voltage v il -0.3 0.3 * v dd v tx high level input current (v i = 4v) i tx -25 -80 -200 m a tx low level input current (v i = 1v) i tx -100 -320 -800 m a MC33889 system basis chip with low speed fault tolerant can interface 8 rx pin high level output voltage rx (i 0 = -250 m a) v oh v dd1 - 0.9 v dd1 v low level output voltage (i 0 = 1.5ma) v ol 0 0.9 v canh, canl pins differential receiver, recessive to dominant threshold (by definition, v diff =v canh -v canl ) v diff1 -3.2 -2.5 v differential receiver, dominant to recessive threshold (bus failures 1, 2, 5) v diff2 -3.2 -2.5 v canh recessive output voltage tx = vdd ; r (rth) < 4k v canh 0.2 v canl recessive output voltage tx = vdd ; r (rtl) < 4k v canl v dd1 - 0.2 v canh output voltage, dominant tx = 0v; i canh = -40ma; normal operating mode v canh v dd1 - 1.4 v canl output voltage, dominant tx = 0v; i canl = 40ma; normal operating mode v canl 1.4 v canh output current (v canh = 0 ; tx = 0) i canh 50 75 100 ma canl output current (v canl = 14v; tx = 0) i canl 50 90 130 ma detection threshold for short-circuit to battery voltage (normal mode) v canh , v canl 7.3 7.9 8.9 v detection threshold for short-circuit to battery voltage (standby/sleep mode) v canh v bat /2 +3 v bat /2+5 v canh output current (sleep mode; v canh = 12v, failure3) 5 10 m a canl output current (sleep mode ; v canl = 0v ; v bat = 12v, failure 4) i canl 0 2 m a canl wake up voltage threshold v wake,l 2.5 3.3 3.9 v canh wake up voltage threshold v wake,h 1.2 2 2.7 v wake up threshold difference (hysteresis) v wakel -v wakeh 0.2 v canh single ended receiver threshold (failures 4, 6, 7) v se, canh 1.5 1.85 2.15 v canl single ended receiver threshold (failures 3, 8) v se, canl 2.8 3.05 3.4 v canl pull up current (normal mode, failures 4, 6 and 7) i canl,pu 45 75 90 m a canh pull down current (normal mode, failure 3) i canh,pd 45 75 90 m a receiver differential input impedance canh / canl r diff 100 180 k w differential receiver common mode voltage range v com -10 10 v canh to ground capacitance c canh 50 pf canl to ground capacitance c canl 50 pf c canl to c canh capacitor difference (absolute value) dc can 10 pf rth, rtl pins conditions symbol min typ max unit MC33889 system basis chip with low speed fault tolerant can interface 9 ac characteristics ( v sup from 5.5v to 18v and t j from -40c to 150c unless otherwise noted) note: 1. when vbat is greater than 18v, the wake up thresholds remain identical to the wake up thresholds at 18v. 2. ac characteristics measured according to schematic figure 2. rtl to vdd switch on resistance (i out < -10ma; normal operating mode) r rtl 10 30 50 w rtl to bat switch series resistance (vbat standby mode or sleep mode) r rtl 8 12.5 20 k w rth to ground switch on resistance (i out <10ma; normal operating mode) r rth 10 25 50 w thermal shutdown can module thermal shutdown t sd 165 c canl an d canh slew rates (10% to 90%). rising or falling edges. note2. t sl 3.5 5 10 v/ m s propagation delay tx to rx low. note2. t pdlow 1 2 m s propagation delay tx to rx high. note2. t pdhigh 1 2 m s min. dominant time for wake-up on canl or canh (vbat standby and sleep modes ; v bat = 12v) t wake 8 16 30 m s min. wake time for wake-up (vbat standby and sleep modes ; v bat = 12v) t wake 6 15 30 m s failure 3 detection time (normal mode) t df3 10 60 m s failure 6 detection time (normal mode) t df6 50 400 m s failure 3 recovery time (normal mode) t dr3 10 60 m s failure 6 recovery time (normal mode) t dr6 150 1000 m s failure 4, 7, 8 detection time (normal mode) t df478 0.75 4 ms failure 4, 7, 8 recovery time (normal mode) t dr478 10 60 m s failure 3, 4, 7,8 detection time (vbat standby and sleep modes ; v bat = 12v) t dr347 0.8 8 ms failure 3, 4, 7,8 recovery time (vbat standby and sleep modes ; v bat = 12v) t dr347 2.5 ms minimum hold time for ?go to sleep? command t gts 4 38 m s edge count difference between canh and canl for failures 1, 2, 5 detection (nerr becomes low), (normal mode) e cdf 3 edge count difference between canh and canl for failures 1, 2, 5 recovery (normal mode) e cdr 3 tx permanent dominant timer disable time (normal mode and failure mode) t tx,d 0.75 4 ms tx permanent dominant timer enable time (normal mode and failure mode) t tx,e 10 60 m s conditions symbol min typ max unit MC33889 device description system basis chip with low speed fault tolerant can interface 10 figure2.fdevice signal waveforms figure3.test circuit for ac characteristics t v th(rd) v th(dr) 0.7v cc 0.3v cc t onrx t offrx -5v 0.7v -2.9v 2.2v v rx v diff v tx t offtx canh canl 5v 0v 3.6v 1.4v dominant bit recessive bit recessive bit tx high: recessive bit tx low: dominant bit tx high: recessive bit canh canl r r c c vdd c r = 133ohms c = 1nf MC33889 device description system basis chip with low speed fault tolerant can interface 11 4 device description introduction: the MC33889 is an integrated circuit dedicated to automotive applications. it includes the following functions: - one full protected voltage regulator with 200ma total output current capability. available output current is 100ma at vdd1 external pin. - driver for external path transistor for v2 regulator function. - reset, programmable watchdog function - four operational modes - wake up capabilities: forced wake up, cyclic sense and wake up inputs, can and spi - can low speed fault tolerant physical interface, compatible with motorola mc33388d. 4.1 device supply the device is supplied from the battery line through the vsup pin. an external diode is required to protect against negative transients and reverse battery. it can operate from 4.5v and under the jump start condition at 27v dc. this pin sustains standard automotive voltage conditions such as load dump at 40v. when vsup falls below 3v typical the mc33989 detects it and store the information into the spi register , in a bit called ?batfail?. this detection is available in all operation modes. 4.2 vdd1 voltage regulator vdd1 regulator is a 5v output voltage with total current capability of 200ma. as the v1 regulator supplies the can module, 100ma is available at the vdd1 external outside the circuit. this vdd1 regulator is normally used in the application for the mai n microcontroller supply. it includes a voltage monitoring circuitry associated with a reset function. the vdd1 regulator is fully protected against over current, short-circuit and has over temperature detection warning flags and shutdow n with hysteresis. ouput current can be lower than 200ma due to limited thermal capability of the device once mounted on the printed circuit board. 4.3 v2 regulator v2 regulator circuitry is designed to drive an external path transistor in order to increase output current flexibility. two pin s are used: v2 sense and v2 ctrl. output voltage can be adjusted by an external resistor bridge, in a range from 1.8 to 8v. vsup must be greater than v2 regulator voltage + 1v. target ballast transistor is pnp mjd32c. other pnp transistor might be used, however depending upon pnp gain an external resistor capacitor network might be connected between emitter and base of pnp. 4.4 hs1 vbat switch output hs1 output is a 2 ohms typical switch from vsup pin. it allows the supply of external switches and their associated pull up or pull down circuitry, in conjunction with the wake up input pins for example. output current is limited to 200ma and hs1 is protected against short-circuit and over temperature. hs1 output is controlled from the internal register and spi. it can be activated at regular intervals in sleep mode thanks to internal timer. it can also be permanently turned on in normal or stand-b y modes to drive external loads such as relays or supply peripheral components. in case of inductive load drice exetrnal clamp circuitry must be added. 4.5 functional modes the device has four modes of operation, stand-by, normal, stop and sleep modes. all modes are controlled by the spi. an additional temporary mode called ?normal request mode? is automatically accessed by the device (refer to state machine) after wake up events. special mode and configuration are possible for sofware application debug and flash memory programmation. 4.5.1 normal mode: in this mode both regulators are on and this corresponds to the normal application operation. all functions are available in this mode (watchdog, wake up input reading through spi, hs1 activation, can communication). the software watchdog is running and must be periodically cleared though spi. 4.5.2 standby mode: only the regulator 1 is on. regulator 2 is turned off by disabling the v2 ctrl pin. same functions as in normal mode are available. the watchdog is running. 4.5.3 sleep mode: regulators 1 and 2 are off. in this mode, the mcu is not powered. the sleep current from vsup pin is less than 100ua (excluding can interface sleep current). in this mode, the device can be awakened internally by cyclic sense via the wake up inputs pins and hs1 output, from the forced wake function, the can physical interface, and spi (csb pin). 4.5.4 stop mode regulator 2 is turned off by disabling the v2 ctrl pin. the regulator 1 is activated in a special low power mode which allow to deliver 2 ma. the objective is to maintain the mcu of the application supplied while it is turned into power saving condition (i .e stop or wait mode). in the stop mode, the device supply current from vbat can be as low as 100ua (excluding can interface sleep current). MC33889 device description system basis chip with low speed fault tolerant can interface 12 stop mode is entered through spi. stop mode is dedicated to power the microcontroller when it is in low power mode (stop, pseudo stop, wait etc.). in these mode the mcu supply current is less than 1ma. the mcu can restart its software application very quickly, without the complete power up and reset sequence. when the application is in stop mode (both mcu and sbc), the application can wake up from the sbc side (ex cyclic sense, forced wake up, can message, wake up inputs) or the mcu side (key wake up etc.). when stop mode is selected by spi, stop mode becomes active 20us after end of spi message. the ?go to stop? instruction must be the last instruction executed by the mcu before going to low p ower m ode. in stop mode the software watchdog can be ?running? or ?not running? depending upon selection by spi. refer to spi description, mcr register bit wdstop. in stop mode, sbc wake up capability are identical as in sleep mode. 4.5.4.1 stop mode: wake up from sbc side: when application is in stop mode, it can wake up from the sbc side. when a wake up is detected by the sbc (ex can, wake up input etc.) the sbc turns itself into normal request mode. the wake up is signalled to the mcu through the int pin. int pin i s pulled low for 10us and then returns high. wake up event can be read through the spi registers. 4.5.4.2 stop mode: wake up from mcu side: when application is in stop mode, the wake up event may come to the mcu. in this case the mcu has to signal to the sbc that it has to go into normal mod in order for the vdd1 regulator to be able to deliver full current capability. this is done by a low to high transisiton of the csb pin. csb pin low to high activation has to be done as soon as possible after the mcu. alternatively the l0 and l1 inputs can also be used as wake up from stop mode. 4.5.4.3 software watchdog in stop mode: if watchdog is enabled (register mcr, bit wdstop set), the mcu has to wake up independently of the sbc before the end of the sbc watchdog time. in order to do this t he mcu has to signals the wake to the sbc through the spi wake up (csb pin low to high transition to activated spi wake up). the n the s bc wakes up and j ump into the normal request mode. mcu has to configured the sbc to go to either normal or standby mode. the mcu can then decide to go back again to stop mode. if no mcu wakes up occurs within the watchdog timing, the sbc will activate the reset pin and jump into the normal request mode. the mcu can then be initialized. 4.5.5 normal request mode: this is a temporary mode automatically accessed by the device after a wake up event from sleep or stop mode or after device power up. in this mode the vdd1 regulator is on, v2 is off, the reset pin is high. as soon as the device enters the normal request mode an internal 400ms timer is started. during these 400ms the micro controller of the application must addressed the sbc via spi and configure the watchdog register (tim1 register). this is the condition for the sbc to leave the normal request mode and enter the normal mode and to set the watchdog timer according to configuration done during the normal request mode. if no spi configuration occurs within the 400ms, two cases must be considered: - the ?batfail flag? has not been cleared: in this case the sbc goes to reset mode for 1ms, then return to normal request mode. if no w/d configuration is done within 400ms, the sbc goes to reset again, then normal request etc. - if the ?batfail flag? has been reset, t he sbc will goes back to previous low power mode. for instance if sbc was in sleep mode prior to the wake up it returns to sleep mode and keep the same wake up event configuration. if sbc was in stop mode, it return to stop mode and keep the same wake up event configuration. after an sbc power up (vsup rising from zero to nominal), and if batfail flag is cleared (mcr register read) the default low power mode is sleep mode. ?batfail flag? is a bit which is triggered when vsup is below 3v. this bit is set into the mcr register. it is reset by mcr register read. 4.5.6 reset and watchdog: mode1 and mode 2 (safe mode): the watchdog and reset functions have two modes of operation: mode 1 and mode 2 (mode 2 is also called safe mode). these modes are independent of the sbc modes (normal, stand-by, sleep, stop). mode 1 or mode 2 selection is done through spi (register mcr, bit safe). default mode after reset is mode 1. 4.6 internal clock the device has an internal clock used to generate all timings (reset, watchdog, cyclic wake up, filtering time etc....). 4.7 reset pin a reset output is available in order to reset the microcontroller. two operation modes for the reset pin are available, mode 1 and mode 2 (refer to table for reset pin operation). the reset cause when sbc is in mode 1 are: - vdd1 falling out of range: if vdd1 fall below the reset threshold (parameter rst-th ), the reset pin is pull low until vdd1 return to nominal voltage. - power on reset: at device power on or at device wake up from sleep mode, the reset is maintained low until vdd1 is within its operation range. MC33889 device description system basis chip with low speed fault tolerant can interface 13 - watchdog time out: if the watchdog is not cleared the sbc will pull the reset pin low for the duration of the reset duration time ( parameter: reset-dur). in mode 2, the reset pin is not activated in case of watchdog time out. refer to? table for reset pin operation?for mode detail. for debug purposes at 25c, reset pin can be shorted to 5v. 4.8 software watchdog (selectable window or time out watchdog) software watchdog is used in the sbc normal and stand-by modes for the mcu monitoring. the watchdog can be either window or time out. this is selectable by spi (register tim, bit wdw). default is window watchdog. the period for the watchdog is selectable by spi from 5 to 400ms (register tim, bits wdt0 and wdt1). when the window watchdog is selected, the closed window is the first half of the selected period, and the open window is the second half of the period. the watchdog can only be cleared within the open window time. an attempt to clear the watchdog in the closed window will generate a reset. watchdog is cleared through spi by addressing the tim register. refer to? table for reset pin operation?for operation in mode 2. 4.9 wake up capabilities several wake-up capabilities are available for the device when it is in sleep or stop mode. when a wake up has occurred, the wake up event is stored into the wur or can registers. the mcu can then access to the wake up source. the wake up options are selectable trough spi while the device is in normal or standby mode and prior to go to enter low power mode (sleep or stop mode). 4.9.1 wake up from wake up inputs (l0, l1) without cyclic sense: the wake up lines are dedicated to sense external switches state and if changes occur to wake up the mcu (in sleep or stop modes). the wake up pins are able to handle 40v dc. the internal threshold is 3v typical and these inputs can be used as input port expander. the wake up inputs state can be read through spi (register wur). 4.9.2 cyclic sense wake up (cyclic sense timer and wake up inputs l0, l1) the sbc can wake up upon state change of one of the wake up input lines (l0, l1) while the external pull up or pull down resistor of the switches associated to the wake up input lines are biased with hs1 vsup switch. the hs1 switch is activated in sleep or stop mode from an internal timer. cyclic sense and forced wake up are exclusive. if cyclic sense is enabled the forced up can not be enabled. 4.9.3 forced wake up the sbc can wake up automatically after a pre determined time spent in sleep or stop mode. forced wake up is enabled by setting bit fwu in lpc register. cyclic sense and forced wake up are exclusive. if forced wake up is enabled the cyclic sense can not be enabled. 4.9.4 can wake up the device can wake up from a can message. can wake up cannot be disabled. 4.9.5 spi wake up the device can wake up by the csb pin in sleep or stop mode. wake up is detetced by csb pin transition fromlow to high level. in stop mode this correspond to the condition where mcu and sbc are both in stop mode and when the application wake up events come through the mcu. 4.9.6 system power up at power up the device automatically wakes up. 4.10 spi the complete device control as well as the status report is done through a 8 bits spi interface. refer to spi paragraph. 4.11 can the device incorporates a low speed fault tolerant can physical interface. speed rate is up to 125kbauds. its electrical parameters for the canl, canh, rtl, rth rx and tx pins are compatible with the mc33388d. the state of the can interface is programmable through spi. 4.12 device power up after device or system power up the sbc enter into ?normal request mode?. 4.13 package and thermal consideration the device is proposed in a standard surface mount so28 package. in order to improve the thermal performances of the so28 package, 8 pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board. 4.14 table 1: reset and wdogb operation. mode1 and mode2. table below is the reset and watchdog output mode of operation. two modes (mode 1 and mode 2) are available and are selectable through the spi, safe bit. default operation after reset or power up is mode 1. in both modes reset is active at device power up and wake up. in mode 1: reset is activated in case of vdd1 fall or watchdog not triggered. wdogb output is active low as soon as reset goes low and stays low as long as the watchdog is not properly re-activated by spi. MC33889 system basis chip with low speed fault tolerant can interface 14 in mode 2, safe mode: reset in not activated in case of watchdog failure. wdogb output has same behavior as in mode 1. the wdogb output pin is a push pull st ructure than can drive external component of the application in order for instance t o sig- nal mcu wrong operation. even if it is i nternally turned on (low sate) the r eset pins can be forced to 5v at 25c only, t hanks to its internal limited current drive capability (capability used in flash programming modes). note1: wdogb stays low until the watchdog register is properly addressed through spi. 4.15 application hardware and software debug with the sbc when the sbc is mounted on the same printed circuit board as the mico contoller it supplies, both application software and sbc dedicated rouitne must be debugged. following features allow the user to debug the software by allowing the possiblity to disable the sbc internal software watchdog timer. 4.15.1 first bsc power up, reset pin connected to vdd1 at sbc power up, the vdd1 voltage is provided, but if no spi communication occurs to configure the device in normal mode, a reset occurs every 400ms. in order to allow software debug and avoid mcu reset the reset pin can be connected directly to vdd1 by a jumper. 4.15.2 special debug mode with sowftare watchdog disabled though spi the software watchdog can be disabled through spi. but in order to avoid unwanted watchdog disable and to limit th e risk o f disabling the watchdog during sbc normal operation the watchdog disable has to be done when the ?bat fail flag? is set. the bat fail flag is set when the sbc supply voltage (vsup) has been lower than 3v. this is the case at sbc power up. when this is done, the watchdog of the sbc is disabled, sbc can be used without having to clear the w/d on a regular basis to facilitate software and hardware debug. 4.15.3 mcu flash programming configuration in order to allow the possibility to download software into the application memory (mcu eeprom or flash) the sbc allow the following capabilities: the vdd1 can be forced by an external power supply to 5v and the reset and wdogb outputs by external signal sources to zero or 5v and this without damage. this allow for instance to supply the complete application board by extern al power supply and to apply the correct signal to reset pins. 4.16 gnd shift detection 4.16.1 general when normally working in two-wire operating mode, the can transmission can afford some ground shift between different nodes without trouble. nevertheless, in case of bus failure, the transceiver switches to single-wire operation, therefore workin g with less noise margin. the affordable ground shift is decreased in this case. the sbc provides a ground shift detection for diagnosis purpose. four ground shift levels are selectable and the detection is stored in the ior register which is accessible via the spi. events mode wdogb output reset output device power up 1 or 2 (safe mode) low low to high - vdd1 normal - watchdog properly triggered 1 high high vdd1 < rst-th 1 high low watchdog time out reached 1 low (note1) low - vdd1 normal - watchdog properly triggered 2 (safe mode) high high vdd1 < rst-th 2 (safe mode) high low watchdog time out reached 2 (safe mode) low (note1) high MC33889 system basis chip with low speed fault tolerant can interface 15 4.16.2 detection principle the gnd shift to detect is selected via the spi out of 4 different vaues (-0.5v, -1v, -1.5v, -2v). at each tx falling edge (e nd of recessive state) canh voltage is sensed. if it is detected to be below the selected gnd shift threshold, the bit shift is set at 1 in ior register. no filter is implemented. required filtering for reliable detection should be done by software (e.g. several tri als). figure4.reset and wdogb function diagram in mode 1 and 2 reset wdogb vdd1 spi spi csb watchdog time out watchdog register addressed watchdog period w/d clear mode 1 reset mode 2 MC33889 system basis chip with low speed fault tolerant can interface 16 5 table of operation the table below describe the sbc operation modes. the table below describes the sbc special debug mode and flash programming configuration mode voltage regulator hs1 switch wake up capabilities (if enabled) reset pin int software watchdog can cell normal request vdd1: on v2: off hs1: off low for 1ms, then high term vbat normal vdd1: on v2: on hs1 controllable normally high. active low if w/d or vdd1 under voltage occur (and mode 1 selected) if enabled, signal failure (vdd pre warning temp, can, hs1) running term vbat tx/rx rec only standby vdd1: on v2: off hs1 controllable normally high. active low if w/d or vdd1 under voltage occur if enabled, signal failure (vdd temp, can, hs1) running term vbat tx/rx rec only stop vdd1: on (2ma c apability) v2: of f hs1: off or cyclic can (always enable) spi and l0,l1 cyclic sense or forced wake up normally high. active low if w/d or vdd1 under voltage occur signal sbc wake up (not maskable) - running if enabled - not running if disabled term vbat. sleep vdd1: off v2: off hs1 off or cyclic can (always enable spi and l0,l1 cyclic sense forced wake up low not active no running term vbat. tableau 1 : table of operation mode voltage regulator reset and wdogb pins software watchdog mode enter and comment debug vdd1: on v2: on - watchdog is normally high. active only if vdd1 under voltage occurs - wdogb pin function identical as in other modes. not running - mode entered by spi command, while batfail flag is still set. - all sbc functions are available with the exception of the software watchdog which is disabled . flash progra mming forced externally forced externally not running - vsup pin can be power or unpowered. - vdd1, reset and wdogb pin are forced by external power supply or signal sources. sbc mcu = flash vdd reset wdogb external supply and sources applied to vdd1, reset vsup (0 or 12v) simplified connection used in flash programming mode and wdogb test points on application circuit board. programming bus MC33889 system basis chip with low speed fault tolerant can interface 17 6 simplified state machine comment: (1): sbc wake up: wake up from can, lx, cyclic sense or forced wake up. (2): spi wake up: wake up from csb pin (wake up through mcu activity). (3): vdd1 falls: vdd1 falls below vdd1 reset threshold (4): w/d failure: watchdog not triggered before time out, or watchdog trigger in the closed window. (5): in stop mode when sbc wakes up, wake up is transmitted to mcu through int pin activation. int stays low until int register is read (cleared). (6): in stop mode, if w/d is enabled, when sbc goes out of stop mode before w/d time out, w/d timer is stopped. then the normal request mode 400ms timer starts. if no spi configuration occurs within the 400ms sbc goes back to stop mode with same conditions (wake up, w/d enable etc.). (7): in stop mode when mcu goes out of its low power mode, this event is transmitted to sbc through an spi wake up (csb pin activation). (8): in case of short circuit or over load condition at vdd. sbc goes to sleep mode after 100ms. (9): in reset mode vdd1 is on and can deliver full current capability (120ma). reset pulse occurs at reset pin. (10): batfail bit is set to 1 when vsup fall below 3v typical. (11): batfail is reset when mcr register is read. sleep normal request - sbc initialization - reset low 1ms - then reset high - duration 400ms normal standby stop no w/d config < 400ms & previous mode was sleep & batfail bit previously read (batfail reset) (11) spi : - w ake up config . - w /d on or of f - s top spi : - w ake up config . - s leep vdd1 falls (3) or w/ d failure (4) no w/d config < 400ms & previous mode was stop & batfail bit previously read (batfail reset) (11) unpowered (vsup =0) sbc power up , batfail flag set (10) vdd1 fall (3) or w/d time out (if enabled) vdd1 falls(3) or w/d failure (4) spi : - normal mode reset(9) sbc wake up (1)/ int active, w/d timer stopped (node 5,6). spi wake up (2,7) w/d config < 400ms spi : - st andby mode & w/d config < 400ms vdd1 < vdd reset & for t>100ms(8) sbc wake up(1) vdd1 > vdd reset and end of reset pulse no w/d config < 400ms & batfail flag unread (not reset).(11) spi : - wake up config - stop spi : - wake up config - sleep MC33889 system basis chip with low speed fault tolerant can interface 18 7 spi interface 7.1 data format description 7.2 list of registers: name adress description comment and usage mcr $ 0 0 0 mode control register write: control of normal, standby, sleep, stop, debug modes read: batfail flag and other status bits and flags r cr $ 0 0 1 reset control register write: configuration of reset voltage level and safe bit can $ 0 1 0 can control register write: can module control: tx/rx, rec only, term vbat, normal and extended modes read: can wake up and can failure status bits ior $ 0 1 1 i/o control register write: hs1 (high side switch) control in normal and standby mode. gnd shift register level selection read: hs1 over temp bit shift bit (gnd shift above selection) wur $ 1 0 0 wake up input register write: control of wake up input polarity read: wake up input, and real time lx input state tim $ 1 0 1 timing register write: tim1, watchdog timing control, window or timeout mode. write: tim2, cyclic sense and force wake up timing selection lpc $ 1 1 0 low power mode control register write: hs1 periodic activation in sleep and stop modes force wake up control intr $ 1 1 1 interrupt register write: interrupt source configuration read: int source table 7-1. mosi miso bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 d0 d1 d2 d3 r/w a0 a1 a2 data address read operation: r/w bit = 0 write operation: r/w bit = 1 MC33889 system basis chip with low speed fault tolerant can interface 19 7.3 register description 7.3.1 mcr register control bits status bits 7.3.2 rcr register control bits mcr d3 d2 d1 d0 $000b w wdsleep mctr2 mctr1 mctr0 r batfail vddtemp gfail wdrst reset 0 0 0 0 table 7-2. batfail mctr2 mctr1 mctr0 sbc mode description x automatically entered after reset normal request 0 0 0 1 normal 0 0 1 0 standby x 0 1 1 stop 0 1 0 0 sleep 1 1 0 1 normal for debugging only, watchdog is disabled 1 1 1 0 standby wdstop watchdog in stop mode 0 off 1 on status bit description gfail logic or of can, hs1 failure batfail battery fail flag vddtemp temperature pre-warning on vdd (latched) wdrst watchdog reset occured rcr d3 d2 d1 d0 $001b w safe rstth r reset 0 0 table 7-3. MC33889 system basis chip with low speed fault tolerant can interface 20 7.3.3 can register some description. fault tolerant can transceiver standard modes (light version only) the can transceiver standard mode can be programmed by setting cext to 0. the transceiver cell will then be behave as known from mc33388.. fault tolerant can transceiver extended modes (light version only) by setting cext to 1 the transceiver cell supports sub bus communication. condition safe wdogb reset device power up 0 1 0 0 ? 1 v1 normal, wd is properly triggered 0 1 1 1 1 v1 drops below 4.5 volt 0 1 1 1 0 0 wd time out 0 1 0 0 1 table 7-4. rstth reset threshold voltage [v] can d3 d2 d1 d0 $001b w cext cctr1 cctr0 r canwu txf canlf canhf reset 0 0 0 table 7-5. cext cctr1 cctr0 mode 0 0 0 termvbat 0 0 1 0 1 0 rxonly 0 1 1 rxtx table 7-6. cext cctr1 cctr0 mode 1 0 0 termvbat 1 0 1 termvdd table 7-7. MC33889 system basis chip with low speed fault tolerant can interface 21 description. status bits 7.3.4 ior register some description. control bits control bit for gnd shift detection) 1 1 0 rxonly 1 1 1 rxtx cext cctr1 cctr0 mode status bit description canwu can wake-up occured txf permanent dominant tx * canlf failure on canl (open wire, short circuit) * canhf failure on canh (open wire, short circuit) * *. light version only ior d 3 d2 d1 d0 $011b w hs1on gslr1 gslr0 r hs1ot shift reset 0 0 0 0 table 7-8. hs1on hs1 0 hs1 switch turn off 1 hs1 switch turn on table 7-9. gslr1 gslr0 typical gnd shift level 0 0 -0.5 v 0 1 -1 v 1 0 -1.5 v 1 1 -2 v table 7-10.gnd shift selection cext cctr1 cctr0 mode table 7-7. MC33889 system basis chip with low speed fault tolerant can interface 22 status bits once the switch has been turned off because of over temperature, it can be turned on again by setting the appropriate control bit to ?1?. 7.3.5 wur register the local wake-up inputs l0 and l 1 can be used in both normal and standby mode as port expander and for waking up the sbc in sleep or stop mode. the wake-up inputs can be configured almost separetly, where l0 and l1 are independed configurable from l2 and l3. control bits: . status bits: status bit description hs1ot high side 1 overtemperature wur d3 d2 d1 d0 $100b w lctr3 lctr2 lctr1 lctr0 r l1wu l0wu reset 0 0 0 0 table 7-11. lctr3 lctr2 lctr1 lctr0 l0 configuration l1 configuration x x 0 0 inputs disabled x x 0 1 high level sensitive x x 1 0 low level sensitive x x 1 1 both level sensitive 0 0 x x inputs disabled 0 1 x x high level sensitive 1 0 x x low level sensitive 1 1 x x both level sensitive table 7-12. status bit description l0wu wake up occured at l0 (sleep or stop mode). logic state on l0 (standby or normal mode) l1wu wake up occured at l1 (sleep or stop mode). logic state on l1 (standby or normal mode) MC33889 system basis chip with low speed fault tolerant can interface 23 7.3.6 tim register description. description 7.3.7 tim2 register the purpose of tim2 register is to select an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching on or off hs1 * . tim1 d3 d2 d1 d0 $101b w 0 wdw wdt1 wdt0 r reset 0 0 0 table 7-13. wdw wdt1 wdt0 watchdog timing [ms] 0 0 0 10 no window watchdog 0 0 1 50 0 1 0 100 0 1 1 400 1 0 0 10 window watchdog enabled (window lenght is half the watchdog timing) 1 0 1 50 1 1 0 100 1 1 1 400 table 7-14. tim2 d3 d2 d1 d0 $101b w 1 csp2 csp1 csp0 r reset 0 0 0 table 7-15. *. only available on mc33890 window closed window open wd timing * 50% wd timing * 50% MC33889 system basis chip with low speed fault tolerant can interface 24 7.3.8 lpc register csp2 csp1 csp0 cyclic sense timing [ms] 0 0 0 5 0 0 1 10 0 1 0 20 0 1 1 40 1 0 0 75 1 0 1 100 1 1 0 200 1 1 1 400 table 7-16. lpc d3 d2 d1 d0 $110b w lx2hs1 fwu hs2auto hs1auto r reset 1 0 0 0 table 7-17. lx2hs1 hs2auto hs1auto wake-up inputs sup- plied by hs1 autotiming hs2 autotiming hs1 x x 0 off x x 1 on x 0 x off x 1 x on table 7-18. cyclic sense timing cyclic sense on time t hs1 sample 100 m s MC33889 system basis chip with low speed fault tolerant can interface 25 7.3.9 intr register control bits: when the mask bit has been set, intb pin goes low if the appropriate condition occurs. status bits: ------------------------------------------------------------------------------------------------------------------------- 0 x x no 1 x x yes intr d3 d2 d1 d0 $111b w hs1ot vddtemp canf r hs1ot vddtemp canf reset 0 0 0 table 7-19. control bit description canf mask bit for can failures vddtemp mask bit for vdd medium temperature hs1ot mask bit for hs1 over temperature status bit description canf can failure vddtemp vdd medium temperature hs1ot hs1 over temperature lx2hs1 hs2auto hs1auto wake-up inputs sup- plied by hs1 autotiming hs2 autotiming hs1 table 7-18. MC33889 how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : motorola japan ltd.; sps, technical information center, 3-20-1, p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 minami-azabu, minato-ku, tokyo 106-8573 japan. 81-3-344-3569 technical information center: 1-800-521-6274 asia / pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. 852-26668334 home page : http://www.motorola.com/semiconductors motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represent ation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motor ola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola pr oducts are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain l ife, or for any application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola produc ts for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors har mless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or un authorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the parts. motorola and are registered tr ademarks of motorola, inc. motorola, inc. is an equal employment opportunity/affirmative action employer. MC33889/d motorola and the stylized m logo are registered in the us patent & trademark office. all other products or service names are the property of their respective owners. ? motorola, inc. 2001. |
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